1. Level (Type) of work: Qualifying Degree/Master thesis


2. Topic: Design of electronic block for acquisition and accumulation of data from multiwire position-sensitive detectors with individual data readout from each wire.


3. Work objective: To develop architecture and schematic circuit diagram of the block taking into account realization of all logical operations in FPGA; to design a printed circuit board.


4. Minimum required time: 1 year


5. Supervisors: PhD Levchanoskii Feodosii Vasilyevich


6. Contact phone number and e-mail:

63612, This email address is being protected from spambots. You need JavaScript enabled to view it.